Tri-state Elastic Buffer Design
نویسندگان
چکیده
For the recent CMOS feature sizes power dissipation becomes an overriding concerns for VLSI circuit design. We propose a novel approach named tri-state elastic buffer design which reduces the total power, area & delay of elastic buffer. The paper presents a design and implementation of tristate buffer mechanism in 120 nm technology. This design offers also the advantage of third state (High Impedance state) of tri-state buffer. The proposed elastic buffer design using tri-state buffer is implemented in DSCH & MICROWIND tools. The obtained result shows that our design is effective in terms 48.68 % reduction in total power, 5.62 % reduction in delay & 40.98 %
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